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| INTEGRATED CIRCUITS DATA SHEET TDA5155 Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads Preliminary specification File under Integrated Circuits, IC11 1997 Apr 08 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads CONTENTS 1 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.6.1 8.6.2 8.6.3 8.7 8.7.1 8.7.2 8.7.3 8.7.4 8.7.5 8.7.6 8.7.7 8.7.8 8.7.9 8.7.10 8.8 8.9 9 10 11 12 13 14 15 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Read mode Write mode Sleep mode Standby mode Active mode Bi-directional serial interface Addressing Programming data Reading data Operation of the serial interface Configuration Power control Head select Servo write Test Write amplifier programmable capacitors High frequency gain attenuator register High frequency gain boost register Settle pulse Address registers summary Head unsafe HUS survey LIMITING VALUES HANDLING THERMAL RESISTANCE RECOMMENDED OPERATION CONDITIONS CHARACTERISTICS DEFINITIONS LIFE SUPPORT APPLICATIONS TDA5155 1997 Apr 08 2 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 1 FEATURES 3 GENERAL DESCRIPTION TDA5155 * Designed for 10 dual-stripe MR-read/inductive write heads * Current bias-current sense architecture * Single supply voltage (5.0 V 10%); a separate write drivers supply pin can be biased from VCC to 8 V +10% * MR elements connected to ground (GND) * Equal bias currents in the two MR stripes of each head * On-chip AC couplings eliminate MR head DC offset * 3-wire serial interface for programming * Programmable voltage/current mode write data input * Programmable high frequency zero-pole gain boost * Programmable write driver compensation capacitance * Programmable MR bias currents and write currents * 1-bit programmable read gain * Sleep, standby, active and test modes available * Measurement of head resistances in test mode * In test mode, one MR bias current may be forced to a minimum current * Short write current rise and fall times with near rail-to-rail voltage swing * Head unsafe pin for signalling of abnormal conditions and behaviour * Low supply voltage write current inhibit (active or inactive) * Support servo writing * Provide temperature monitor * Thermal asperity detection with programmable threshold level * Requires only one external resistor. 2 APPLICATIONS The 5.0 V pre-amplifier for HDD applications has been designed for five terminal, dual-stripe Magneto-Resistive (MR)-read/inductive write heads. The disks of the disk drive are connected to ground. To avoid voltage breakthrough between the heads and the disk, the MR elements of the heads are also connected to ground. The symmetry of the dual-stripe head-amplifier combination automatically distinguishes between the differential signals such as signals and the common-mode effects like interference. The latter are rejected by the amplifier. The device incorporates read amplifiers, write amplifiers, a serial interface, digital-to-analog converters, reference and control circuits which all operate on a single supply voltage of 5 V 10%. The output drivers have a separate supply voltage pin which can be connected to a higher supply voltage of up to 8 V +10%. The complementary output stages of the write amplifier allow writing with near rail-to-rail peak voltages across the inductive write head. The read amplifier has low input impedance. The DC offset between the two stripes of the MR head is eliminated using on-chip AC coupling. Fast settling features are used to keep the transients short. As an option, the read amplifier may be left biased during writing so as to reduce the duration of these transients even further. Series inductance in the leads between the amplifier and MR heads influences the bandwidth which can be compensated by using a programmable high frequency gain boost (HF zero). HF noise and bandwidth can be attenuated using a programmable high frequency gain attenuator (HF pole). On-chip digital-to-analog converters for MR bias currents and write currents are programmed via a 3-wire serial interface. Head selection, mode control, testing and servo writing can also be programmed using the serial interface. In sleep mode the CMOS serial interface is operational. Fig.1 shows the block diagram of the device. * Hard Disk Drive (HDD). 4 ORDERING INFORMATION TYPE NUMBER TDA5155X PACKAGE NAME - naked die DESCRIPTION VERSION - 1997 Apr 08 3 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 5 QUICK REFERENCE DATA PARAMETER supply voltage supply voltage for write drivers differential voltage gain from head inputs to RDx, RDy; RMR = 28 ; IMR = 10 mA data bit d4 = 0 data bit d4 = 1 B-3dB F Virn CMRR -3 dB frequency bandwidth noise figure input referred noise voltage common mode rejection ratio RMR mismatch <5% upper bandwidth without gain boost (4 nH lead inductance) RMR = 28 ; IMR = 10 mA; Tamb = 25 C; f = 20 MHz RMR = 28 ; IMR = 10 mA; Tamb = 25 C; f = 20 MHz IMR = 10 mA f < 1 MHz f < 100 MHz PSRR IMR = 10 mA power supply rejection ratio (input referred) RMR mismatch <5% f < 1 MHz f < 100 MHz tr, tf write current rise/fall time (10% to 90%) Lh = 150 nH; Rh = 10 ; IWR = 35 mA; f = 20 MHz VCC(WD) = 8.0 V VCC(WD) = 6.5 V IMR(PR) IWR(b-p) fSCLK programming MR bias current range programming write current range (base-to-peak) serial interface clock rate Rext = 10 k Rext = 10 k - - 5 20 - - - - - - - - - - 45 25 80 50 - - - - - 160 226 220 3.0 0.9 CONDITIONS MIN. 4.5 VCC TYP. 5.0 8.0 TDA5155 SYMBOL VCC VCC(WD) Gv(dif) MAX. 5.5 8.8 UNIT V V - - - 3.2 1.0 MHz dB nV/Hz - - - - dB dB dB dB 1.8 2.1 20.5 51 25 ns ns mA mA MHz 1997 Apr 08 4 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 6 BLOCK DIAGRAM TDA5155 handbook, full pagewidth VCC 16 VCC(WD) (5 to 8 V) 1 TDA5155 WDlx(i) WDly(i) WDlx(v) WDly(v) 6 7 4 5 WRITE DRIVER INPUT FF 20, 25, 30, 35, 40, 45, 50, 55, 60, 65 10 19, 24, 10 29, 34, 39, 44, 49, 54, 59, 64 nWy nWx HUS 3 HEAD UNSAFE INDICATOR LOW SUPPLY VOLTAGE INDICATOR Rext 17 WRITE CURRENT SOURCE 10 VOLTAGE REFERENCE +VCC TAS DETECTOR SERIAL INTERFACE 20 k 4 5 3 10 head select 10 WRITE DRIVER AND READ PREAMP (10x) 8 R/W SCLK SEN SDATA 11 9 5 4 4 13 RDx RDy 14 RMR CURRENT SOURCE 23, 28, 33, 38, 43, 48, 53, 58, 10 63, 68 22, 27, 32, 37, 42, 47, 52, 57, 10 62, 67 21, 26, 31, 36, 41, 46, 51, 56, 10 61, 66 nRy nGND nRx 2, 12, 15, 18 MGG982 GNDn Fig.1 Block diagram. 1997 Apr 08 5 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 7 PINNING DESCRIPTION supply voltage for the write drivers ground connection 1 head unsafe output write data input (differential, voltage input) write data input (differential, voltage input) write data input (differential, current input) write data input (differential, current input) read/write (read = active HIGH, write = active LOW) serial bus enable serial bus data serial bus clock ground connection 2 read data output (differential x - y) read data output (differential x - y) ground connection 3 supply voltage 10 k external resistor ground connection 4 inductive write head connection for head H0 (differential x - y) inductive write head connection for head H0 (differential x - y) MR-read head connection for head H0 (differential x - y) ground connection for head H0 MR-read head connection for head H0 (differential x - y) inductive write head connection for head H1 (differential x - y) inductive write head connection for head H1 (differential x - y) MR-read head connection for head H1 (differential x - y) ground connection for head H1 MR-read head connection for head H1 (differential x - y) inductive write head connection for head H2 (differential x - y) SYMBOL PAD 2Wy 2Rx 2GND 2Ry 3Wx 3Wy 3Rx 3GND 3Ry 4Wx 4Wy 4Rx 4GND 4Ry 5Wx 5Wy 5Rx 5GND 5Ry 6Wx 6Wy 6Rx 6GND 6Ry 7Wx 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 TDA5155 SYMBOL PAD VCC(WD) GND1 HUS WDIx(v) WDIy(v) WDIx(i) WDIy(i) R/W SEN SDATA SCLK GND2 RDx RDy GND3 VCC Rext GND4 0Wx 0Wy 0Rx 0GND 0Ry 1Wx 1Wy 1Rx 1GND 1Ry 2Wx 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 DESCRIPTION inductive write head connection for head H2 (differential x - y) MR-read head connection for head H2 (differential x - y) ground connection for head H2 MR-read head connection for head H2 (differential x - y) inductive write head connection for head H3 (differential x - y) inductive write head connection for head H3 (differential x - y) MR-read head connection for head H3 (differential x - y) ground connection for head H3 MR-read head connection for head H3 (differential x - y) inductive write head connection for head H4 (differential x - y) inductive write head connection for head H4 (differential x - y) MR-read head connection for head H4 (differential x - y) ground connection for head H4 MR-read head connection for head H4 (differential x - y) inductive write head connection for head H5 (differential x - y) inductive write head connection for head H5 (differential x - y) MR-read head connection for head H5 (differential x - y) ground connection for head H5 MR-read head connection for head H5 (differential x - y) inductive write head connection for head H6 (differential x - y) inductive write head connection for head H6 (differential x - y) MR-read head connection for head H6 (differential x - y) ground connection for head H6 MR-read head connection for head H6 (differential x - y) inductive write head connection for head H7 (differential x - y) 1997 Apr 08 6 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads SYMBOL PAD 7Wy 7Rx 7GND 7Ry 8Wx 8Wy 8Rx 55 56 57 58 59 60 61 DESCRIPTION inductive write head connection for head H7 (differential x - y) MR-read head connection for head H7 (differential x - y) ground connection for head H7 MR-read head connection for head H7 (differential x - y) inductive write head connection for head H8 (differential x - y) inductive write head connection for head H8 (differential x - y) MR-read head connection for head H8 (differential x - y) SYMBOL PAD 8GND 8Ry 9Wx 9Wy 9Rx 9GND 9Ry 62 63 64 65 66 67 68 TDA5155 DESCRIPTION ground connection for head H8 MR-read head connection for head H8 (differential x - y) inductive write head connection for head H9 (differential x - y) inductive write head connection for head H9 (differential x - y) MR-read head connection for head H9 (differential x - y) ground connection for head H9 MR-read head connection for head H9 (differential x - y) 9GND 8GND 9Wy 9Wx 8Wy 8Wx 7Wy 55 68 VCC(WD) GND1 HUS WDIx(v) WDIy(v) WDIx(i) WDIy(i) R/W SEN SDATA SCLK GND2 RDx RDy GND3 VCC Rext GND4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 67 66 65 64 63 62 61 60 59 58 57 56 54 7Wx 9Ry 9Rx 8Ry 8Rx 7Ry 7Rx handbook, full pagewidth 7GND 53 52 51 50 49 48 47 46 45 6Ry 6GND 6Rx 6Wy 6Wx 5Ry 5GND 5Rx 5Wy 5Wx 4Ry 4GND 4Rx 4Wy 4Wx 3Ry 3GND 3Rx 3Wy 3Wx TDA5155 44 43 42 41 40 39 38 37 36 35 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 0GND 1GND 2GND 0Wx 0Wy 0Rx 0Ry 1Wx 1Wy 1Rx 1Ry 2Wx 2Wy 2Rx 2Ry 0 MGG981 Fig.2 Pad arrangement. 1997 Apr 08 7 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 8 8.1 FUNCTIONAL DESCRIPTION Read mode 8.2 Write mode TDA5155 The read mode disables the write circuitry to save power while reading. The read circuitry is disactivated for write, sleep and standby modes. The read circuitry may also be biased during write mode to shorten transients. The selected head is connected to a multiplexed low-noise read amplifier. The read amplifier has low-impedance inputs nRx and nRy (n is the number of the head) and low-impedance outputs RDx and RDy. The signal polarity is non-inverting from x and y inputs to x and y outputs. Ambient magnetic fields at the MR elements result in a relative change in MR resistance: dR MR -------------R MR This change produces a current variation: dR MR dI MR = I MR x -------------- , R MR where IMR is the bias current in the MR element. The current variation is amplified to form the read data output signal voltage, which is available at RDx and RDy. AC coupling between MR elements and amplifier stages prevents the amplifier input stages from overloading by DC voltages across the MR elements. A fast settling procedure shortens DC settling transients. An on-chip generated stable temperature reference voltage (1.32 V), available at the Rext pin, is dropped across an external resistor (10 k) to form a global reference current for the write and the MR bias currents. The MR bias current DACs are programmed through the serial interface according to the following formula: 10k I MR = 0.5 x -------------- ( 10 + 16d4 + 8d3 + 4d2 + 2d1 + d0 ) R ext (in mA), where d4-d0 are bits (either logic 0 or logic 1). At power-up all bits are set to logic 0, which results in a default MR current of 5 mA. The adjustable range of the MR currents is 5 mA to 20.5 mA. The MR bias currents are equal for the two stripes of each head. The gain amplifier is 1-bit programmable. The amplifier gain can be set to its nominal value or to the nominal value +3 dB. To minimize power dissipation, the read circuitry may be disabled in write mode. The write circuitry is disabled in read, sleep and standby modes. In write mode, a programmable current is forced through the selected two-terminal inductive write head. The push-pull output drivers yield near rail-to-rail voltage swings for fast current polarity switching. The write data input can be either voltage or current input (see Chapter 12). In voltage mode, the differential write data inputs WDIx(v) and WDIy(v) are PECL (Positive Emitter Coupled Logic) compatible. The write data flip-flop can either be used or passed-by. In the case that the write data flip-flop is used, current polarity is toggled at the falling edges of V WDIx ( v ) - V WDIy ( v ) V data = ----------------------------------------------------2 Switching to write mode initializes the data flip-flop so that the write current flows in the write head from x to y. In the case that the write data flip-flop is not used, the signal polarity is non-inverting from x and y inputs to x and y outputs. The write current magnitude is controlled through on-chip DACs. The write current is defined as follows: 10k I WR = -------------- ( 20 + 16d4 + 8d3 + 4d2 + 2d1 + d0 ) R ext (in mA), where d4-d0 are bits (either logic 0 or logic 1). The adjustable range of the write current is 20 mA to 51 mA. At power-up, the default values d4 = d3 = d2 = d1 = d0 = logic 0 are initialized, corresponding to IWR = 20 mA. IWR is the current provided by the write drivers: the current in the write coil and in the damping resistor together. The static current in the write coil is I WR ---------------- , Rh 1 + -----Rd where Rh is the resistance of the coil including leads and Rd is the damping resistor. 1997 Apr 08 8 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 8.3 Sleep mode TDA5155 In sleep mode, the device is accessible via the serial interface. All circuits are inactive, except the circuits of the CMOS serial interface and the circuitry which forces the data registers to their default values at power-up and which fixes the DC level of outputs RDx and RDy (required when operating with more than one amplifier). Typical static current consumption is -30 A. Dynamic current consumption during operation of the serial interface in sleep mode due to external activity at the inputs to the serial interface is not included. In all modes, including the sleep mode, data registers can be programmed. Sleep is the default mode at power-up. Switching to other modes takes less than 0.1 ms. 8.4 Standby mode Three phases in the communication are distinguishable: addressing, programming and reading. Each communication sequence starts with an addressing phase, followed by either a programming phase or a reading phase. 8.6.1 ADDRESSING The circuit can be put in standby mode using the serial interface. In standby mode, the typical DC current consumption is 330 A. Transients from standby mode to active mode are two orders of magnitude shorter than from sleep mode to active mode. This is important in the case of cylinder mode operation with multiple amplifiers. All amplifiers can operate from standby mode and all head switch times can be kept just as short as in the case of operation with a single amplifier. Head switch times are summarized in the switching characteristics. 8.5 Active mode When SEN goes HIGH, bits are latched in at rising edges of SCLK. The first eight bits a7 to a0 (starting with a0) are shifted serially into an address register. If SEN goes LOW before 16 bits have been received, the operation is ignored. When more than 16 bits (address and data) are latched in before SEN goes LOW, the first 8 bits are interpreted as an address and the last 8 bits as data. SEN should go HIGH at least 5 ns before the first rising edge of SCLK. Data should be valid at least 5 ns before and after a rising edge of SCLK. The first six bits a5 to a0 constitute the register address. Bit a6 is unused. If bit a7 = logic 0, a PROGRAMMING sequence starts. If bit a7 = logic 1, READING data from the pre-amplifier can start. 8.6.2 PROGRAMMING DATA Active mode is either read mode or write mode depending on the status of the R/W pin. 8.6 Bi-directional serial interface If a7 = 0, the last eight bits d7 to d0 before SEN goes LOW are shifted into an input register. When SEN goes LOW, the communication sequence is ended and the data in the input register is copied in parallel to the data register that corresponds to the decoded address a0 to a5. SEN should go LOW at least 5 ns after the last rising edge of SCLK. See Fig.3 for the timing diagram of the programming. 8.6.3 READING DATA The serial interface is used for programming the device and for reading of status information. 16 bits (8 bits for data and 8 for address) are used to program the device. The serial interface requires 3 pins: SDATA, SCLK and SEN. These pins (and R/W as well) are CMOS inputs. The logic input R/W has an internal 20 k pull-up resistor and the SEN logic input has an internal 20 k pull-down resistor. Thus, in case the SEN line is opened, no data will be registered and in case the R/W line is opened, the device will never be in write mode. SDATA: serial data; bi-directional data interface. In all circumstances, the LSB is transmitted first. SCLK: serial clock; 25 MHz clock frequency. SEN: serial enable; data transfer takes place when SEN is HIGH. When SEN is LOW, data and clock signals are prohibited from entering the circuit. Immediately after the IC detects that a7 = logic 1, data from the data register (address a5 to a0) is copied in parallel to the input register. Two wait clock cycles must follow before the controller can start inputting data. At the first falling edge of SCLK after the 2 wait rising edges of SCLK, the LSB d0 is placed on SDATA line followed by d1 at the next falling edge of SCLK etc. If SEN goes LOW before 8 address bits (a7 to a0) have been detected, the communication is ignored. If SEN goes LOW before the 8 data bits have been sent out of the IC, the reading sequence is immediately interrupted. See Fig.4 for the timing diagram of the reading via the serial interface. 1997 Apr 08 9 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads TDA5155 handbook, full pagewidth SEN SCLK SDATA a0 a1 a2 a3 a4 a5 a6 0 d0 d1 d2 d3 data MGG983 d4 d5 d6 d7 address Fig.3 Timing diagram of the write sequence of the serial interface operation (a7 = logic 0). handbook, full pagewidth SEN SCLK SDATA a0 a1 a2 a3 a4 a5 a6 1 d0 d1 d2 d3 d4 d5 d6 d7 address wait cycles data MGG984 Fig.4 Timing diagram of the read sequence of the serial interface operation a7 = logic 1). 1997 Apr 08 10 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 8.7 Operation of the serial interface 8.7.2 POWER CONTROL TDA5155 The serial interface programming is summarized in Section 8.7.10. 8.7.1 d0: By default (d0 = logic 0), write data passes from the write data input via the data flip-flop to the write driver. The write driver toggles the current in the head at the falling edges of: V WDIx ( v ) - V WDIy ( v ) V data = ----------------------------------------------------- or 2 I WDIx ( i ) - I WDIy ( i ) I data = ---------------------------------------------2 When d0 = logic 1, the write data flip-flop is not used. The signal polarity is non-inverting from the inputs WDIx and WDIy to the outputs nWx and nWy. d1: By default (d1 = logic 0), the pre-amplifier senses PECL write signals at WDIx(v) and WDIy(v). When d1 = logic 1, the pre-amplifier senses input write currents at WDIx(i) and WDIy(i). d2: By default (d2 = logic 0), the write current is inhibited under low supply voltage conditions. The write current inhibit is made inactive by programming d2 to logic 1. d3: By default (d3 = logic 0), in write mode low supply voltage, open head, and other conditions are monitored and flagged at HUS. If d3 = logic 1, HUS is LOW in write mode and HIGH in read mode. d4: The amplifier read gain may be programmed in the configuration register. By default (d4 = logic 0), the read gain is typically 160 with RMR = 28 . If d4 = logic 1, the read amplifier gain is 3 dB higher (226 in this case). d5: In order to minimize the write-to-read recovery times, the first stage of the read amplifier may be kept biased during write mode. By default, (d5 = logic 0) the read amplifier is powered down during write mode, and the fast settling procedure is activated after write-to-read switching. If d5 = logic 1 the read amplifier is kept biased during write mode, and the fast settling procedure still occurs if the head is changed or the MR current is re-programmed. 1997 Apr 08 11 CONFIGURATION By default, d1 = d0 = logic 0, the pre-amplifier powers up in sleep mode. If d1 = logic 0, d0 = logic 1 or d1 = logic 1, d0 = logic 0 the circuit goes in standby mode. If d1 = d0 = logic 1, the circuit goes in active mode (read or write mode depending on the R/W input). 8.7.3 HEAD SELECT Selection of a wrong head (H10-H15) causes an head unsafe condition. HUS goes HIGH when in write mode a wrong head is selected and when d3 in the configuration register is LOW. When in read mode and a wrong head is selected, head H0 is therefore selected and if d3 in the configuration register is LOW, HUS goes LOW. 8.7.4 SERVO WRITE The circuit is prepared for servo writing. However, the device will not be guaranteed. 8.7.5 TEST d2 = d1 = d0 = logic 0. The circuit is not in test mode. This is the default situation. 8.7.5.1 MR head test d2 = logic 0, d1 = logic 0, d0 = logic 1. In read mode, the voltages at Rx and Ry (at the top of the MR elements) of the selected head are fed to outputs RDx and RDy. By measuring the output voltages single ended at two different IMR currents, the MR resistance can be accurately measured according to the following formula: V RDx1 - V RDx2 R MRx = -------------------------------------- for the x-side. I MRx1 - I MRx2 Open head and head short-circuited-to-ground conditions can therefore be detected. d2 = logic 0, d1 = logic 1, d0 = logic 0. Same as before, with the difference that IMR2 is fixed to a minimum constant value of 5 mA. Measuring in the same way as above with IMR1 > 5 mA, enables the detection of MR elements shorted together. 8.7.5.2 Temperature monitor d2 = logic 0, d1 = logic 1, d0 = logic 1. The temperature monitor voltages are connected to RDx and RDy. The output differential voltage depends on the temperature according to: dV = -0.00364 x T + 1.7; 0 < T < 140 C. The temperature may be measured with a typical precision of 5 C. Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 8.7.5.3 Thermal asperity detector TDA5155 d2 = logic 1, d1 = x, d0 = (0,1). Unlike the above tests, the thermal asperity detection does not use the RDx and RDy outputs. Thus, the reader is fully operational. In case a thermal asperity is detected, it is flagged at the HUS pin. The threshold voltage for the thermal asperity detection is 2-bit programmable. These 2 bits consist of d0 (LSB) of the test mode register (address = 0xxx0110), and d2 of the compensation capacitor register (address = 0xxx0111). V th = ( 210 + 560.d0 + 280.d2 ) V d0 of test mode register; d2 of the compensation capacitor register. 8.7.6 WRITE AMPLIFIER PROGRAMMABLE CAPACITORS frequency noise. The HF pole can be used in combination with the HF zero in order to boost the HF gain locally and yet limit the very high frequency noise enhancement. 8.7.8 HIGH FREQUENCY GAIN BOOST REGISTER By default (d3 = d2 = d1 = d0 = logic 0) the high frequency gain boost is not active. The gain boost provides a zero which allows to optimize the bandwidth of the read amplifier and to correct for attenuation caused by series inductances in the leads between the MR heads and the read amplifier inputs. 8.7.9 SETTLE PULSE By default (d2 = d1 = d0 = logic 0) the programmable capacitors are zero. These capacitors are used to improve the performance of the write amplifier according to the write amplifier output load. 8.7.7 HIGH FREQUENCY GAIN ATTENUATOR REGISTER By default (d2 = d1 = d0 = logic 0) the settle pulse has a nominal duration of 3 s. Its value can be programmed from 2.125 s to 3 s according to the following formula: 1 t st = 2s + ------------------------------------------------------------------ s ( 4.d2 + 2.d1 + 1.d0 + 1 ) The settle pulse is used to shorten the transients during switching. By default (d3 = d2 = d1 = d0 = logic 0) the high frequency gain attenuator is not active. The gain attenuator provides a pole which limits the bandwidth and reduces the high 8.7.10 ADDRESS REGISTERS SUMMARY FUNCTION A7 A6 A5 A4 A3 A2 A1 A0 0 X X X 0 0 0 0 configuration register: d0 = 0: use data flip-flop; d0 = 1: by-pass data flip-flop d1 = 0: WDI PECL; d1 = 1: current input d2 = 0: write current inhibit active; d2 = 1: write current inhibit inactive read mode: d3 = 0: HUS active; d3 = 1: HUS HIGH write mode: d3 = 0: HUS active; d3 = 1: HUS LOW d4 = 0: read gain nominal; d3 = 1: read gain +3 dB d5 = 0: read amplifier OFF during write mode; d5 = 1: read amplifier ON during write mode 0 X X X 0 0 0 1 power control register: (d1,d0) = (0,0): sleep mode (d1,d0) = (1,0) or (0,1): standby mode (d1,d0) = (1,1): active mode (write or read) 0 X X X 0 0 1 0 head select register: (d3,d2,d1,d0) = (0,0,0,0) to (1,0,0,1): H0 to H9 addressing H10 to H15 causes HUS to go HIGH if in write mode and H0 to be selected if in read mode ADDRESS REGISTERS(1) 1997 Apr 08 12 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads ADDRESS REGISTERS(1) FUNCTION A7 A6 A5 A4 A3 A2 A1 A0 0 X X X 0 0 1 1 TDA5155 MR current DAC register: 10k I MR = 0.5 x -------------- ( 10 + 16.d4 + 8.d3 + 4.d2 + 2.d1 + d0 ) mA R ext write current DAC register: 10k I WR = -------------- ( 20 + 16.d4 + 8.d3 + 4.d2 + 2.d1 + d0 ) mA R ext servo write register: (d0,d1) = (0,0): one head (d0,d1) = (1,1): all heads (d0,d1) = (1,0): odd numbered heads (H1, H3, H5, H7 and H9) (d0,d1) = (0,1): even numbered heads (H0, H2, H4, H6 and H8) 0 X X X 0 1 0 0 0 X X X 0 1 0 1 0 X X X 0 1 1 0 test mode register: (d2,d1,d0) = (0,0,0) = not in test mode (d2,d1,d0) = (0,0,1) = read head test (IMR1 = IMR2) (d2,d1,d0) = (0,1,0) = read head test (IMR2 = 5 mA fixed) (d2,d1,d0) = (0,1,1) = temperature monitor (d2,d1,d0) = (1,X,d0) = thermal asperity detection, see note 2 Vth = (210 + 560.d0 + 280.d2) V 0 0 X X X X X X 0 1 1 0 1 0 1 0 compensation capacitor register: equivalent differential capacitance = (4.d2 + 2.d1 + 1.d0) x 2 pF high frequency gain attenuator register 800 MHz nominal pole frequency = -------------------------------------------------------------------8.d3 + 4.d2 + 2.d1 + 1.d0 0 X X X 1 0 0 1 high frequency gain boost register 800 MHz nominal zero frequency = -------------------------------------------------------------------8.d3 + 4.d2 + 2.d1 + 1.d0 0 X X X 1 0 1 0 settle time register 1 settle time: t st = 2s + ------------------------------------------------------------------ s ( 4.d2 + 2.d1 + 1.d0 + 1 ) 1 1 X X X X X X 1 a3 1 a2 1 a1 1 a0 device ID register ID = 8.d3 + 4.d2 + 2.d1 + 1.d0; d3 to d0 are preset to (0,0,1,1) when a7 = 1, data from the register with address a3 to a0 is read out on SDATA Notes 1. Unused bits in the registers (indicated by X) are don't care. Default data, initialized at Power-up, is zero in all registers. For VCC <2.5 V, the register contents are not guaranteed. 2. Vth programming uses both the test mode register and the compensation capacitor register. d0 in the formula above is the LSB of the test mode register and d2 is the d2 data bit of the compensation capacitor register. 1997 Apr 08 13 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 8.8 Head unsafe TDA5155 The HUS pin is an open collector output. Therefore when the pin is not connected to an external pull-up resistor, HUS is LOW. HUS pins can be connected together in case of operation with more than one amplifier. It is used to detect abnormal or unexpected operation. Sleep mode: HUS is HIGH, to permit working with more than one amplifier. Standby mode: HUS is HIGH, to permit working with more than one amplifier. Read mode: * If in the configuration register d3 = 1, HUS is HIGH * If in the configuration register d3 = 0, HUS goes LOW for: - Selection of a wrong head (H10 to H15)(1) - Rext pin open, short-circuited to ground or to VCC (read current too low or too high) - Low VCC and VCC(WD) conditions. A low supply voltage detector is placed close to the VCC and VCC(WD) pins. Detection of low VCC (main supply): a VCC supply voltage below 4.0 V 5% is flagged at the HUS pin. The voltage detection range is then 4.2 to 3.8 V with an hysteresis of 110 mV 10%. Detection of low VCC(WD) (write drivers supply): a fault will be flagged at the HUS pin if VCC(WD) drops 0.8 V 10% below VCC. One must be aware that such a detection is only aimed to warn for a catastrophic situation. Indeed, VCC(WD) should never be below VCC. 8.9 HUS survey HUS MODE Sleep mode Standby mode Active mode - - Read Test mode: HUS is HIGH except when the TAS detector is ON. If a thermal asperity is detected, HUS goes LOW. Servo write mode: HUS is LOW. Write mode: * If in the configuration register d3 = 1, HUS is LOW * If in the configuration register d3 = 0, HUS goes HIGH for: - Selection of a wrong head (H10 to H15)(1) - Rext pin open, short-circuited to ground or to VCC (write current too low or too high) - Write Data Input frequency too low (WDIx-WDIy) - Write head Wx, Wy open, Wx or Wy short-circuited to ground(2) - Write driver still left biased while not selected - Low VCC and VCC(WD) conditions (write current inhibit can be active or inactive). The same detector is used for read and write mode. The write current may be inhibited if d2 = 0 in the configuration register. The HUS line indicates an unsafe condition as long as the fault is present, in read mode as well as in write mode. It indicates again a safe condition only 0.5 s to 1 s after the last fault has disappeared. (1) Head numbers 0 to 9 are correct, 10 to 15 are signalled as unsafe. (2) Switching to write mode makes HUS LOW. After the transient the HUS detection circuitry is activated. The target for the head open detection time is 15 ns. DATA BIT D3 STATE - - Read mode A-test mode(1) TAS mode Write Write mode A-test mode(1) Servo mode(2) 0 HIGH HIGH ACTIVE HIGH ACTIVE ACTIVE HIGH LOW 1 HIGH HIGH HIGH HIGH ACTIVE LOW HIGH LOW Notes 1. A-test mode = analog test mode. 2. In servo mode, the performance of the IC is not guaranteed. 1997 Apr 08 14 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 9 LIMITING VALUES TDA5155 In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC VCC(WD) Vn1 supply voltage write driver supply voltage PARAMETER -0.5 -0.5 MIN. MAX. +6.0 +9.5 +5.5 VCC + 0.5 +8.8 +1 0.1 +150 150 V V V V V V A C C UNIT voltage on all pins except VCC(WD), read inputs nRx, nRy -0.5 and write driver outputs nWx, nWy (n = 0 to 9) absolute maximum value - -0.5 - -0.5 - -65 - voltage on write driver outputs nWx, nWy absolute maximum value voltage on read inputs nRx, nRy ground current (pins nGND) storage temperature junction temperature Vn2 Vn3 InGND Tstg Tj VCC(WD) + 0.5 V 10 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. 11 THERMAL CHARACTERISTICS The thermal resistance depends on the flex used. The TDA5155X is shipped in naked dies form. 1997 Apr 08 15 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 12 RECOMMENDED OPERATION CONDITIONS SYMBOL VCC VCC(WD) VIH VIL Vi(dif)(p-p) VIH(PECL) VIL(PECL) Ii(dif)(p-p) IIH(dif) IIL(dif) Tamb Tj RMR (RMR) Ll(tot) Rl(tot) VMR Vsig(dif)(p-p) Lwh Rwh Cwh Rext PARAMETER supply voltage write driver supply voltage HIGH level input voltage (CMOS) LOW level input voltage (CMOS) differential input voltage (peak-to-peak value) HIGH level PECL input voltage LOW level PECL input voltage differential input current (peak-to-peak value) HIGH level differential input current LOW level differential input current ambient temperature junction temperature MR element resistance RMR mismatch total lead inductance to the head total lead resistance to the head voltage on top of MR elements differential MR head input voltage (peak-to-peak value) write head inductance write head resistance write head capacitance external reference resistor including lead; note 6 including lead; note 6 including lead; note 6 I ref V ref = ---------R ext note 5 in each lead; note 6 in each lead; note 6 note 7 reading writing (VCC(WD) = 8 V) note 3 note 3 note 3 note 4 note 4 note 4 CONDITIONS note 1 note 2 MIN. 4.5 VCC 3.5 0 0.4 - 1.5 0.4 -1.4 - 0 - - 15 - - - - 0.4 - - - - - - - - 0.7 2.85 2.15 0.8 -1.2 -0.4 - - - 28 - 25 1.5 - 1 0.15 10 tbf 10 TYP TDA5155 MAX. 5.5 8.8 VCC 0.8 1.5 VCC - 1.0 - -0.1 70 110 130 34 4 - - 0.5 2 - - - - UNIT V V V V V V V mA mA mA C C C nH V mV H pF k 1997 Apr 08 16 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads Notes to the recommended operating conditions 1. A supply by-pass capacitor from VCC to ground or a low pass filter may be used to optimize the PSRR. 2. The supply voltage VCC(WD) must never be below VCC in normal mode, and two diode 1.4 V above VCC in servo mode. 3. The given values should be interpreted in the way that the single ended voltage could swing from 0.2 to 0.75 V, and that the common mode voltage should be such that for any of the two states, the VIH(PECL) is less than VCC and VIL(PECL) is more than 1.5 V. PECL voltage swing: a wider peak-to-peak voltage swing can be used. In that case a current will flow through the WDI inputs. This current is approximately WDIx ( v ) - WDIy ( v ) - 1.4 equal to -----------------------------------------------------------------------200 TDA5155 4. Same comments for the given values as for the voltage input mode. The HIGH (respectively LOW) level input current is defined such that it produces the same effect at the output of the writer (Wx, Wy) as the HIGH (resp. LOW) level input voltage. 5. The mismatch refers to the resistance of the two stripes of the same head. This is defined as follows: (RMR) = abs(RMR1 - RMR2). 6. These parameters depend on the head model. The data given in the table are those used for testing. 7. The combination of maximum head resistance, lead resistance and bias current is not permitted. To avoid voltage breakthrough between heads and disk, the voltage over the MR elements is limited by two diode voltages. 1997 Apr 08 17 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 13 CHARACTERISTICS VCC = 5.0 V; VCC(WD) = 8 V; VGND = 0 V; Tamb = 25 C; unless otherwise specified. SYMBOL Read characteristics IMR IMR Gv(dif) MR current adjust range tolerance (excluding Rext) differential voltage gain; note 1 Rext = 10 k; 0.5 mA steps IMR programmed at 10 mA from head inputs to RDx, RDy; RMR = 28 ; IMR = 10 mA; f = 20 MHz d4 = 0 d4 = 1 Ri(dif) Ci(dif) THD BL BH differential input resistance differential input capacitance total harmonic distortion lower signal gain pass-band -3 dB edge higher signal gain pass-band edge -3 dB; note 2 without gain boost (4 nH lead inductance) with gain boost (50 nH lead inductance) F Virn BF(L) noise figure RMR = 28 ; IMR = 10 mA; Tamb = 25 C; f = 20 MHz - - - - - 220 170 3.0 0.9 - - - IMR = 10 mA - - - - - - 160 226 13 16 1 - - - - - - 5 - - 4 PARAMETER CONDITIONS MIN. TYP. TDA5155 MAX. UNIT 20.5 - mA % pF % kHz 100 MHz MHz dB nV/Hz kHz 3.2 1.0 400 input referred noise voltage; RMR = 28 ; IMR = 10 mA; note 3 Tamb = 25 C; f = 20 MHz lower noise band edge (+3 dB) upper noise band edge (+3 dB) channel separation; note 4 RMR = 28 ; IMR = 10 mA; Tamb = 25 C; no lead inductance RMR = 28 ; IMR = 10 mA; Tamb = 25 C; no lead inductance unselected head BF(H) - 220 - MHz cs PSRR CMRR - - - 50 80 50 - - - dB dB dB power supply rejection ratio; f < 1 MHz; IMR = 10 mA note 5 f < 100 MHz; IMR = 10 mA common mode rejection ratio; note 5 from nRx-nRy to RDx-RDy RMR mismatch < 5% IMR = 10 mA f < 1 MHz f < 100 MHz - - 45 25 - - dB dB 1997 Apr 08 18 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads SYMBOL DR PARAMETER rejection ratio of SCLK and SDATA; note 6 CONDITIONS from SCLK, SDATA inputs to the - RDx-RDy outputs; a 200 mV (peak-to-peak) signal is applied to SCLK or SDATA inputs at 25 MHz, and measurement is performed at RDx-RDy DC voltage between RDx and RDy single ended - MIN. TYP. 50 - TDA5155 MAX. UNIT dB VO(R)(dif) output DC offset voltage in read mode (differential after DC settling) output impedance in read mode maximum differential output current common mode output voltage in read mode common mode DC supply rejection ratio in read mode differential output impedance in other modes (write, standby, sleep) - 0.2 V Zo(R) Io(max)(dif) Vo(cm) V o ( cm ) --------------------V CC Zo(n)(dif) - - 16 4 1.5 20 - - 2.0 - - mA V dB RDx, RDy 1.0 - - 50 k Write characteristics IWR IWR Vs(max)(p-p) Ro(dif) Co(dif) tr, tf write current adjust range (in the write drivers) tolerance (excluding Rext) maximum voltage swing (peak-to-peak value) differential output resistance differential output capacitance write current rise/fall time without flip-flop (10% to 90%); note 7 not including the head capacitance Lh = 150 nH; Rh = 10 ; IWR = 35 mA; f = 20 MHz VCC(WD) = 8.0 V VCC(WD) = 6.5 V tas tpd write current rise/fall time asymmetry; note 8 propagation delay 50% of (WDIx/WDIy) to 50% of (Wx, Wy) channel separation percentage of tr or tf (tr or tf and logic asymmetry) write head short-circuited, data flip-flop by-passed not-selected head - - - - - - - - 1.8 2.1 5 5 ns ns % ns Rext = 10 k; 1 mA steps IWR programmed at 35 mA VCC(WD) = 5 V VCC(WD) = 8 V (differential) 20 - - - - - 35 7 - - 200 5 51 - 8 13 - - mA % V V pF cs - 45 - dB 1997 Apr 08 19 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads SYMBOL PARAMETER CONDITIONS - - MIN. - 200 TYP. TDA5155 MAX. UNIT Switching characteristics fSCLK Vo(cm) serial interface clock rate common mode DC output IMR = 10 mA; IWR = 35 mA voltage change from read to write mode write-to-read recovery time (AC and DC settling); note 9 from 50% of the rising edge of R/W to steady state read-back signal: AC and DC settling at 90% (without load at RDx, RDy) read amplifier OFF: d5 = 0 read amplifier ON: d5 = 1 tsw(R) head switching (in read mode), standby to read active and MR current change recovery time. (AC and DC settling); note 10 read amplifier off time write settling times; note 11 from falling edge of SEN to steady state read-back signal (without load at RDx, RDy) - - - 3 100 3 4.5 150 4.5 s ns s 25 - MHz mV trec(W-R) toff(R) tst(W) from falling edge of R/W to read head inactive from 50% of the falling edge of R/W to 90% of the steady state write current (in write mode) from rising edge of R/W to 10 x IWR (programmed) (IWR = 35 mA) 1 - - - - 50 70 ns ns toff(W) write amplifier off time - - 50 ns tsw(W) head switching (in write from falling edge of SEN to write - mode), and standby to write head active head active switch time to and from sleep mode - 50 70 ns tsw(S) - 100 s DC characteristics ICC(R) ICC(W) read mode supply current write mode supply current IMR = 10 mA; note 12 IWR = 35 mA; note 13 from VCC (5 V) from VCC(WD) (5 to 8 V) IDD(STB) IDD(S) Vref standby mode supply current sleep mode supply current reference voltage for Rext static - - - - - 33 54 0.25 -0.02 1.32 41 61 1 - - mA mA mA mA V - 72 80 mA 1997 Apr 08 20 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads Notes to the characteristics 1. The differential voltage gain depends on the MR resistance. It can be improved by programming the d4 bit in the configuration register. 2. The gain boost implements a pole-zero combination: The +3 dB gain boost corner frequency is 800 MHz -------------------------------------------------------------------- . The -3 dB gain 8.d3 + 4.d2 + 2.d1 + 1.d0 attenuation corner frequency is 800 MHz -------------------------------------------------------------------- , where d3, d2, d1 and d0 8.d3 + 4.d2 + 2.d1 + 1.d0 are to be programmed via the serial interface. In practical use, the bandwidth is limited by the inductance of the connection between the MR heads and the pre-amplifier. 3. Noise calculation a) Definitions: The amplifier has a low input resistance. No lead resistance is taken into account. The input referred noise voltage, excluding the noise of the MR resistors, is defined V no 2 2 as: ( V irn ) = -------- - 4kT x ( R MR1 + R MR2 ) , Gv where Gv is the voltage gain, Vno is the noise voltage at the output of the amplifier, k is the Boltzmann constant and T is the temperature in K. The noise figure is defined as follows: V no 2 -------Gv F = 10 x log ----------------------------------------------------------- in 1 Hz 4kT x ( R MR1 + R MR2 ) bandwidth. Note that RMR includes all resistances between Rx or Ry to ground. b) Noise figure versus IMR and RMR: Table 1 shows the variation of the noise figure with IMR and RMR. c) Input referred noise voltage: The input referred noise voltage calculation can be significantly different (from 1.0 to 0.44 nV/Hz for instance) by taking an equivalent signal-to-noise ratio into account when using two MR stripes (28 for each stripe) or one MR stripe (42 ). It assumes that the signal coming from the head is larger for a dual-stripe head than for a single-stripe head (50% extra signal for a dual-stripe head). 4. The channel separation is defined by the ratio of the gain response of the amplifier using the selected head H(n) to the gain response of the amplifier using the adjacent head H(n 1), head H(n) being selected. 5. TDA5155 The PSRR (in dB) is defined as input referred ratio: Gv PSRR = 20 x log ------ , where Gv is the differential input Gp to differential output gain, and Gp is the power supply to differential output gain.The CMRR (in dB) is defined Gv as input referred ratio: CMRR = 20 x log ---------- , where G cm Gv is the differential input to differential output gain and Gcm is the common mode input to differential output gain. Flex and board lay-out may affect these parameters significantly. 6. This refers to the crosstalk from SCLK and SDATA inputs via the read inputs to RDx and RDy. Two cases can be distinguished: a) When SEN is LOW, SCLK and SDATA are prohibited reaching the device and crosstalk is low. b) Programming via the serial interface is done with SEN HIGH. Then crosstalk can occur. A careful design of the board or flex-foil is required to avoid crosstalk via this path. 7. The rise and fall times depend on the write amplifier/write head combination. Lh and Rh represent the components on the evaluation board. Parasitic capacitances also limit the performance. 8. The write current rise/fall time asymmetry is defined by tr - tf ---------------------2 ( tr + tf) 9. Write-to-read recovery time includes the write mode to read mode switching using the R/W pin on the same head (see Fig.5). The AC signal reaches its full amplitude few tens of ns after appearing at the reader RDx and RDy outputs. 10. In read mode, the head switching, standby to read active switching and changing MR current include fast current settling (see Fig.5). The AC signal reaches its full amplitude few tenth of ns after appearing at the reader RDx and RDy outputs. 11. Write settling time includes the read mode to write mode switching using the R/W pin. 12. The typical supply current in read mode depends on the bias current for the MR element. 13. The typical supply current in write mode also depends on the write current. 1997 Apr 08 21 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads Table 1 Noise figure F (dB) RMR () 20 25 30 IMR = 7 mA 2.7 2.8 2.9 IMR = 10 mA 2.9 3.0 3.1 TDA5155 IMR = 15 mA 3.1 3.3 3.5 handbook, full pagewidth R/W RDx-RDy trec(W-R) toff(R) MGG985 Fig.5 Timing diagram of the reader: write-to-read switching on the same logic head. handbook, full pagewidth SEN RDx-RDy tsw(R) MGG986 Fig.6 Timing diagram of the reader: typical head, current and standby-to-read characteristics. 1997 Apr 08 22 Philips Semiconductors Preliminary specification Pre-amplifier for Hard Disk Drive (HDD) with MR-read/inductive write heads 14 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values TDA5155 This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 15 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. 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Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997 Internet: http://www.semiconductors.philips.com SCA54 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 297027/20/01/pp24 Date of release: 1997 Apr 08 Document order number: 9397 750 01427 |
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